1. Field of the Invention
The present invention relates to an apparatus for decoding BCH code suitable for use in a wide variety of data communications.
2. Description of the Prior Art
The assignee of the present application has previously proposed an apparatus for decoding BCH (Bose-ChaudhuriHocquenghem) code suitable for being formed as a large scale integrated (LSI) circuit (see Japanese Laid-open Patent Gazette No. 61-281720, and corresponding U.S. Pat. No. 4,751,704). This previously-proposed BCH code decoding apparatus is constructed as shown in FIG. 1.
In FIG. 1, a received sequence is applied to an input terminal 1. The received sequence is supplied to an S1 forming circuit 2 and an S3 forming circuit 3 and the syndromes S1 and S3 are formed. The syndromes S1 and S3 are supplied to a zero detecting circuit 4. The zero detecting circuit 4 generates a detection signal of a low level "L" when all of the digits of the syndromes S1 and S3 are "O", namely, when no error is detected. This detection signal is supplied into a latch circuit 4A synchronously with the receiving sequence.
The syndrome S1 is supplied to an S1.sup.2 forming circuit 5 and an S1.sup.3 forming circuit 6 and the values of S1.sup.2 and S1.sup.3 are produced. The S1.sup.3 forming circuit 6 multiplies S1.sup.2 with S1 to produce S1.sup.3 as will be explained hereinafter. The syndromes S3 and S1.sup.3 are supplied to an arithmetic operating circuit 7, by which (S1.sup.3 +S3) is formed.
In this manner, the respective coefficients S1, S1.sup.2 s1.sup.3 and S3 of the error-location polynomial .sigma.'(X) are obtained and supplied to a Chien search circuit 8 for performing the process of Chien search. The Chien search circuit 8 is shown as the region surrounded by the broken line in FIG. 1 and comprises: arithmetic operating circuits 9 and 12; delay circuits 10 and 13, each having the delay time of one clock pulse; switching circuits 11 and 14; an adding circuit 15; and a zero detecting circuit 16. The switching circuits 11 and 14 respectively select the syndromes S1 from the S1 forming circuit 2 and S1.sup.2 from the S1.sup.2 forming circuit 5 at the timing of the head bit of the receiving sequence. The switching circuits 11 and 14 respectively select outputs of the delay circuits 10 and 13 with respect to the remaining bits. Control of the switching circuits 11 and 14 is accomplished by a conventional circuit for generating timing control signals, operating in synchronism with the receiving sequence.
Outputs of the switching circuits 11 and 14 are supplied to the arithmetic operating circuits 9 and 12, respectively. Outputs of the operating circuits 9 and 12 are supplied to the delay circuits 10 and 13, respectively. In this way, the cyclic constitution is obtained. The operating circuit 9 multiplies .alpha..sup.-2 and the operating circuit 12 multiplies .alpha..sup.-1. .alpha. is the root of the generator polynomial over GF(2.sup.n). Assuming that a code length is n, the term of S1.alpha..sup.-2n is obtained by the operating circuit 9 and the term of S1.sup.2 .alpha..sup.-n is derived by the operating circuit 12. The outputs of the operating circuits 9 and 12 are supplied to the adding circuit 15 to perform the addition of 30 (mod. 2).
The adding circuit 15 executes the arithmetic operation of the error-location polynomial (.sigma.'(X)=S1x.sup.2 +S1.sup.2 x+S1.sup.3 +S3). An output of the adding circuit 15 is supplied to the zero detecting circuit 16. The position where the output of the adding circuit 15 becomes zero is the error location. The zero detecting circuit 16 generates a correction instructing signal which becomes a high level "H" at the error location.
The correction instructing signal from the zero detecting circuit 16 is supplied to an AND gate 17 together with an output of the latch circuit 4A. The output of the latch circuit 4A becomes a low level "L", due to the zero detecting circuit 4, when all digits of both of the syndromes S1 and S3 are "0". When (S1=S3=0), the result of the operation of the error-location polynomial 15 becomes zero, so that the correction instructing signal which signals an error is generated from the zero detecting circuit 16. The AND gate 17 is provided to inhibit an improper correction instructing signal.
The correction instructing signal of "H" from the AND gate 17 is supplied to an exclusive OR gate (hereinafter referred to as EX-OR gate) 18. The bits of the receiving sequence from a shift register 19 are inverted by the EX-OR gate 18 in response to the correction instructing signal which is generated in correspondence to the error location, so that the bit errors are corrected. The error-corrected data sequence from the EX-OR gate 18 is taken out to an output terminal 20. The shift register 19 delays the receiving sequence by the period of time necessary for detection of the error location.
The invention can be applied to decode, for example, the (15, 7) BCH code, which (15) denotes the code length and (7) is the information bit length and the minimum distance is 5. Therefore, the errors of two bits or less can be corrected. The generator polynomial of this code is ##EQU1## Assuming that .alpha. is the root of (x.sup.4 +x+1=0), the minimal polynomial having as the root is (x.sup.4 +x.sup.3 +x.sup.2 +x+1). The elements over the Galois Field GF(2.sup.4) which is given by (x.sup.4 x+1)=0 are as follows.
______________________________________ .alpha..sup.3 .alpha..sup.2 .alpha..sup.1 .alpha..sup.0 ______________________________________ 0 0 0 0 0 .alpha..sup.0 0 0 0 1 .alpha..sup.1 0 0 1 0 .alpha..sup.2 0 1 0 0 .alpha..sup.3 1 0 0 0 .alpha..sup.4 0 0 1 1 .alpha..sup.5 0 1 1 0 .alpha..sup.6 1 1 0 0 .alpha..sup.7 1 0 1 1 .alpha..sup.8 0 1 0 1 .alpha..sup.9 1 0 1 0 .alpha..sup.10 0 1 1 1 .alpha..sup.11 1 1 1 0 .alpha..sup.12 1 1 1 1 .alpha..sup.13 1 1 0 1 .alpha..sup.14 1 0 0 1 ______________________________________ The parity-check matrix H of this code is shown below. ##STR1## The apparatus for decoding BCH code according to the prior art can not
To solve this problem, it is proposed in the case of transmitting digital data that an error correction code of high redundancy is employed when a condition of transmission line is not good; and an error correction code of low redundancy is employed when a condition of transmission line is good. Thus, when the redundancy of error correction code is low, the remaining portion of the error correction code is used to transmit other digital data.
Depending on the kinds of information to be transmitted, it is requested either to increase error correction capability or to increase error detection capability even if the error correction capability is low. For example, when data for a computer is transmitted, error correction capability has to be increased because data for the computer needs accuracy. When digital audio data is transmitted, error detection capability has to be increased in order to compensate for data by interpolation of the preceding and succeeding data.
If redundancy or capability of BCH code is changed, a plurality of decoding apparatus must be provided because the prior-art decoding apparatus of FIG. 1 decodes only one kind of BC code. This provides a large-scaled arrangement of the apparatus.